Design Guide
AI Accelerator HDI PCB Design
BGA escape routing, sequential lamination and power delivery for AI boards.
AI accelerator boards — the PCBs that carry GPUs, TPUs, custom ASICs and their supporting memory, power and I/O subsystems — represent the most complex PCB constructions in commercial production. A single AI accelerator module may require 30+ layers on Megtron 7 laminate, sequential HDI with stacked microvias for fine-pitch BGA escape, via-in-pad throughout, controlled impedance for 112G PAM4 SerDes channels, 3-4 oz copper on power planes for 500-700W delivery, and board dimensions exceeding 500 x 300 mm. This article examines the HDI design decisions that make these boards manufacturable.
BGA escape routing at 0.4-0.65 mm pitch
Modern AI processors use BGA packages with 0.5 mm or 0.4 mm ball pitch and 4,000-10,000+ balls. Escape routing from these packages requires HDI with laser-drilled microvias. The inner rows of the BGA cannot be routed to signal layers through standard through-hole vias — there is no space between pads for dog-bone fan-out. Instead, each pad contains a microvia that connects to the next layer down, where a trace routes the signal to a buried via or another microvia that transitions to the target signal layer.
Stacked microvias — two or three laser-drilled vias stacked directly on top of each other through consecutive layer pairs — provide vertical routing without consuming horizontal space. A 3-level stacked microvia connects layer 1 through layer 4 in the footprint of a single pad, enabling escape routing from the deepest interior rows of a dense BGA. Stacked vias require copper filling of each via level before the next level is drilled, adding lamination and plating cycles to the fabrication process.
Sequential lamination and build-up structure
An AI accelerator board with 32 layers and 3-level stacked microvias requires 5 or more sequential lamination cycles. The core layers are fabricated first (drilling, plating, etching), then laminated into a sub-assembly. Additional layers are added in pairs (one on top, one on bottom) with each lamination cycle. After each lamination, laser vias are drilled and plated to connect the new layers to the existing structure. This sequential build-up process is what makes HDI boards expensive — each lamination cycle adds material, labor and process time.
Minimizing the number of sequential lamination cycles is the most effective way to control HDI fabrication cost. An engineer who can escape-route a processor with 2-level stacked vias instead of 3-level saves one lamination cycle per side — potentially reducing fabrication cost by 20-30%. This routing efficiency requires careful planning of the layer assignment, signal escape strategy and power distribution during the stackup design phase.
Laminate selection for 56G/112G
AI accelerator interconnects operate at 56G PAM4 today with 112G PAM4 in current designs. At these data rates, the laminate is the largest single contributor to channel insertion loss. Megtron 6 (Df 0.004 at 12 GHz) supports 56G PAM4 for short-to-medium trace lengths. Megtron 7 (Df 0.002) is specified for 56G channels with longer traces and for all 112G channels. The laminate choice is validated through channel simulation (insertion loss, return loss, crosstalk) using the actual stackup, trace geometry and via structures in the design.
Power delivery for 500-700W processors
Delivering hundreds of watts to a processor requires heavy copper on power and ground planes (3-4 oz), wide power distribution traces, and dense arrays of power vias connecting the VRM output to the processor power balls. The DC resistance of the power delivery path must be low enough to maintain the supply voltage within the processor’s tolerance band at maximum current. IR drop analysis on the actual layout confirms whether the power delivery design is adequate or requires wider traces, more vias or additional copper weight.
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