Controlled impedance PCB
Controlled Impedance PCB: ±8% with TDR Verification
50 Ω single-ended and 85–100 Ω differential targets modeled on your real stack-up with a 2D field solver, held in fabrication by etch and lamination control, and measured by TDR on coupons from every panel.
- Standard tolerance
- ±8%
- Outside ±8%
- DFM review
- Every panel
- TDR
- Common targets
- 50 / 90 / 100 Ω
Overview
What is a controlled impedance PCB?
A controlled impedance PCB holds the characteristic impedance of specified traces, typically 50 Ω single-ended or 85–100 Ω differential, within a stated tolerance. It does this by controlling trace width, dielectric thickness, laminate Dk and copper thickness, and then verifying the result by TDR on test coupons.
At AstroPCB, ±8% is standard. Every target is modeled on the actual stack-up before release, and coupons built on the same panel are measured after fabrication, with a report available for every order.
Why it matters
Why impedance control matters.
A signal travelling down a trace sees that trace’s characteristic impedance. If impedance is uniform, the signal propagates cleanly. Where it changes, because of width variation, dielectric thickness variation or transitions between regions, part of the energy reflects back toward the source. Reflections cause ringing, timing jitter, higher bit-error rates and lost noise margin.
Impedance control is needed whenever the trace is long relative to the signal’s rise time, roughly when trace length exceeds a tenth of the wavelength of the fastest edge. In practice that covers almost every modern interface: USB, PCIe, HDMI, DDR, Ethernet (RGMII, SGMII, 10GbE+), LVDS, MIPI, any SerDes link and all RF interconnects.
What sets impedance
The four parameters that set impedance.
| Parameter | Effect on Z₀ | How it’s controlled |
|---|---|---|
| Trace width | Wider → lower Z₀ | Imaging + etch compensation, AOI measurement |
| Dielectric height to reference | Thicker → higher Z₀ | Core/prepreg selection, press parameters |
| Dielectric constant (Dk) | Higher Dk → lower Z₀ | Named laminate, Dk at operating frequency |
| Copper thickness | Thicker → slightly lower Z₀ | Foil choice, plating control |
Solder mask on outer layers lowers impedance by roughly 1–3 Ω compared with bare microstrip, and etching leaves a trapezoidal cross-section rather than a perfect rectangle. Both are included in our model.
How we control it
How impedance is controlled in manufacturing.
- 01
Model
2D field solver on the real stack-up, using laminate Dk at your frequency.
- 02
Adjust
Trace width or dielectric tuned to hit target; you approve changes.
- 03
Fabricate
Etch compensation, AOI of inner-layer widths, controlled lamination.
- 04
Measure
TDR on coupons from the same panel; report supplied.
The model accounts for laminate Dk at the operating frequency (not just the 1 MHz datasheet value), copper foil type, etch factors and solder-mask loading. In fabrication, dielectric thickness comes from prepreg choice, lay-up and press parameters, and trace width from imaging and etch control, with inner-layer widths checked by AOI before lamination.
Single-ended vs differential
Single-ended vs differential impedance.
Single-ended impedance, typically 50 Ω, applies to a trace referenced to a plane carrying its own signal. Differential impedance, typically 85, 90 or 100 Ω, applies to a pair carrying complementary signals, as in USB, LVDS, PCIe and Ethernet. Differential impedance depends both on each trace’s geometry over the plane and on coupling between the two traces. Tighter spacing increases coupling and lowers differential impedance for a given single-ended geometry. Keep spacing constant along the pair.
Structures
Impedance structures we build.
| Structure | Where | Notes |
|---|---|---|
| Microstrip | Outer layer over one plane | Partly in air; mask lowers Z₀ slightly |
| Embedded microstrip | Under mask or prepreg | Higher effective Dk |
| Stripline / offset stripline | Inner layer between planes | Fully in dielectric; best shielding |
| Edge-coupled differential | Any layer | Spacing sets coupling |
| Coplanar waveguide (GCPW) | Outer layer with side grounds | Common in RF |
Tolerance
What ±8% means.
On a 50 Ω trace, ±8% means a measured 46–54 Ω. The tolerance covers combined variation in trace width (about ±0.5 mil), prepreg thickness (about ±10%), laminate Dk within the lot and copper thickness. Requirements outside the published ±8% reference are reviewed per design and must be confirmed in writing before release. Most interface standards (USB, PCIe, DDR) are written with manufacturing variation of this order in mind, so ±8% is usually enough. Ask for tighter tolerance only on nets where simulation shows you need it.
Common targets
Common impedance targets.
| Interface | Typical target |
|---|---|
| RF, general single-ended | 50 Ω |
| USB 2.0 / 3.x | 90 Ω differential |
| PCIe | 85 Ω differential |
| Ethernet, SATA, most SerDes | 100 Ω differential |
| HDMI, LVDS, MIPI | 100 Ω differential |
| DDR4 / DDR5 | ≈ 40–50 Ω single-ended, ≈ 80–100 Ω differential |
Design guidelines
Design guidelines for controlled impedance.
- Keep trace width constant along each controlled net; minimize neck-downs
- Never route over plane splits, slots or voids
- Keep differential spacing constant and pairs length-matched
- Specify target, tolerance and reference layer(s) per net class on the drawing
- Let the fabricator adjust width to real materials — and approve the change
- Estimate with the impedance calculator; finalize with our stack-up
FAQ
Common questions.
What impedance tolerance can you achieve?
±8% is the published standard; requirements outside this value are reviewed per design. Every order includes TDR verification on coupons.
How do you calculate impedance for my stack-up?
With a 2D field solver using your trace geometry, dielectric thickness, copper weight and the laminate’s Dk at frequency; we can also propose widths for your targets.
What is the most common controlled impedance value?
50 Ω single-ended and 100 Ω differential; USB uses 90 Ω and PCIe 85 Ω differential.
How is impedance verified?
By TDR measurement of coupons fabricated on the same panel, with a report supplied.
Does controlled impedance cost more?
Slightly, for modeling, coupons and testing. It is standard on most multilayer designs.
Why did my fabricator change trace widths?
To hit impedance on the real laminate and stack-up. Changes should be approved before fabrication.
Ready when your files are
Send your design for a capability check.
Upload Gerber, ODB++ or IPC-2581 data. Every quote includes a written engineering DFM review, typically within one business day.