Controlled Impedance PCB

Controlled impedance PCB manufacturing ensures that signal traces maintain a specified characteristic impedance — typically 50 ohms single-ended or 90-100 ohms differential — within a defined tolerance. At AstroPCB, controlled impedance to ±8% is standard, verified by time-domain reflectometry (TDR) measurements on impedance coupons fabricated alongside the production panels.

Why impedance control matters

Every electrical signal traveling on a PCB trace encounters the characteristic impedance of that trace. When the impedance is uniform along the entire trace length, the signal propagates cleanly. When the impedance changes — due to trace width variation, dielectric thickness variation, or transitions between board regions — a portion of the signal energy reflects back toward the source. These reflections degrade signal integrity, cause timing jitter, increase bit error rates and can push a digital interface below its noise margin.

Controlled impedance is required for any interface where the signal rise time is fast enough that the trace length exceeds approximately one-tenth of the signal wavelength. In practice, this includes virtually all modern digital interfaces: USB, PCIe, HDMI, DDR memory buses, Ethernet (RGMII, SGMII, 10GbE+), LVDS, MIPI, and any SerDes link. It also includes all RF and microwave interconnects.

How impedance is controlled in manufacturing

Characteristic impedance depends on four physical parameters: trace width, dielectric thickness between the trace and its reference plane, dielectric constant of the laminate, and copper thickness. The fabricator controls impedance by adjusting trace width and dielectric thickness during the stackup design phase, then maintaining those dimensions within tolerance during fabrication.

Before fabrication begins, the engineering team models the proposed stackup using a 2D field solver to calculate the trace width required for each impedance target on each signal layer. The model accounts for the specific laminate Dk (at the operating frequency, not just the datasheet value), copper foil type, etch compensation factors and solder mask loading on outer layers. The result is a set of trace widths that will produce the target impedance when fabricated to the specified stackup dimensions.

During fabrication, dielectric thickness is controlled through prepreg selection, layup configuration and lamination press parameters. Trace width is controlled through photolithography and etch process parameters, with etch compensation applied to account for the trapezoidal cross-section produced by chemical etching. Inner layer trace widths are measured using automated optical inspection before lamination. After fabrication, impedance coupons on the panel border are measured using TDR to confirm that the finished board meets the impedance specification.

Single-ended vs differential impedance

Single-ended impedance (typically 50 ohms) applies to traces referenced to a ground plane where each trace carries an independent signal. Differential impedance (typically 90 or 100 ohms) applies to paired traces that carry complementary signals — USB, LVDS, PCIe, Ethernet differential pairs. Differential impedance depends on both the trace geometry relative to the reference plane and the coupling between the two traces of the pair. Tighter coupling (smaller trace-to-trace spacing) lowers the differential impedance for a given single-ended geometry.

Impedance tolerance: what ±8% means

A ±8% tolerance on a 50-ohm trace means the measured impedance falls between 46 and 54 ohms. This tolerance accounts for the combined variation in trace width (±0.5 mil typical), dielectric thickness (±10% typical for prepreg), Dk variation within the laminate lot, and copper thickness variation. Tighter tolerances (±5%) are possible but require tighter process controls and may increase cost and lead time. For most digital interfaces, ±8% provides sufficient margin — the interface specifications (USB, PCIe, DDR) are designed with this level of manufacturing variation in mind.

Design guidelines for controlled impedance

Maintain consistent trace width along the entire length of an impedance-controlled net — avoid necking down traces except where absolutely necessary for escape routing, and minimize the length of any necked section. Keep impedance-controlled traces at constant distance from the reference plane — do not route over ground plane splits, slots or void areas. For differential pairs, maintain consistent trace-to-trace spacing. Specify the impedance target, tolerance, and reference layer for each controlled-impedance net class in the fabrication notes.

Request a controlled impedance PCB quote

Upload your design files with impedance requirements noted in the fabrication drawing or README. The engineering team will verify the stackup, run impedance simulation and confirm that the design can be fabricated to your impedance targets.

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