Multilayer PCB Manufacturing

Multilayer PCBs stack four or more copper layers with dielectric insulation between them, providing the routing density, signal integrity and power distribution that complex electronic designs require. From a 4-layer IoT module to a 40-layer AI accelerator board, the principles are the same — copper layers carry signals and power, dielectric layers provide insulation and impedance control, and plated vias connect layers vertically. AstroPCB manufactures multilayer PCBs from 4 to 40+ layers with standard and high-performance laminates, controlled impedance and HDI features.

Why multiple layers are necessary

A circuit with hundreds of connections between dozens of components cannot be routed on two copper layers without making the board impractically large. Adding signal layers provides more routing channels. Adding dedicated ground and power planes provides low-impedance return paths for signals, reduces electromagnetic interference, supplies clean power to components and enables controlled impedance for high-speed interfaces. A typical 6-layer stackup allocates two layers for signal routing, two for ground reference and two for power distribution — the minimum configuration for a moderately complex design with controlled impedance.

Layer count selection

The required layer count depends on signal density (number of connections to route), impedance requirements (which layers need ground references), power delivery requirements (how many voltage rails, what current) and HDI features (blind and buried vias add effective routing layers without increasing the total layer count). A BGA processor with 500 balls on a 0.8 mm pitch board might route on 8 layers. The same processor in a 0.5 mm pitch package with higher pin count might require 12-16 layers with HDI microvias.

More layers increase fabrication cost — each additional layer pair adds material, lamination, drilling, plating and imaging steps. The engineering goal is to use the minimum layer count that satisfies the routing, impedance and power delivery requirements. Sometimes a small board dimension increase or a switch to HDI vias can reduce the layer count, saving more in fabrication cost than the dimensional or HDI change adds.

Stackup design

The stackup defines the sequence of copper and dielectric layers, the dielectric material and thickness of each insulating layer, the copper weight on each layer and the impedance targets for each signal layer. A well-designed stackup provides the required impedance values, adequate power distribution, good signal isolation between layers and a balanced construction that does not warp during lamination or reflow.

Symmetry is critical: the stackup should be symmetric about the center to prevent warping caused by CTE mismatches between copper and dielectric layers. The copper distribution on each layer pair should be roughly balanced — a layer with 80% copper coverage paired with a layer at 20% coverage creates an asymmetric stress that causes bow and twist after lamination.

Lamination and registration

Multilayer fabrication bonds the individual layers together through heat and pressure in a lamination press. The prepreg (pre-impregnated fiberglass cloth with uncured resin) between each layer flows during lamination to fill copper features and bond the layers. Registration — the alignment accuracy between layers — determines whether vias connect properly to pads and whether trace-to-trace spacing is maintained. Standard registration tolerance is ±3 mil (75 microns); HDI designs with microvias require ±2 mil or better.

Request a multilayer PCB quote

Specify layer count, stackup requirements, impedance targets, laminate preference and any HDI features. Upload design files for a DFM-reviewed quotation.

Request a Quote →