PCB Stackup Calculator

Plan multilayer PCB stackups by specifying the copper weight, dielectric material and thickness for each layer. Visualize the cross-section, verify symmetry and estimate total board thickness. A well-designed stackup is the foundation of a successful multilayer PCB — it determines impedance values, signal integrity, power delivery performance, manufacturability and cost.

Stackup design principles

Symmetry: the stackup should be symmetric about the center plane. Asymmetric constructions warp during lamination because different materials and copper densities expand and contract differently. A symmetric stackup balances these stresses, producing a flat board. Example: if the top half has signal-ground-signal-power, the bottom half should mirror it as power-signal-ground-signal.

Reference planes: every high-speed signal layer should have a continuous ground or power plane on at least one adjacent layer. This adjacent plane provides the return current path for the signal and controls the trace impedance. A signal layer without an adjacent reference plane has uncontrolled impedance and poor EMI performance.

Impedance planning: the dielectric thickness between a signal layer and its reference plane, combined with the dielectric constant and trace width, determines the characteristic impedance. Thinner dielectric gives lower impedance for the same trace width. The stackup must be designed to achieve the required impedance targets (typically 50 ohm single-ended, 90-100 ohm differential) with manufacturable trace widths (3 mil minimum for standard, 4-5 mil preferred).

Common stackup configurations

4-layer: signal/ground/power/signal — the minimum configuration for controlled impedance. Suitable for simple designs with moderate routing density. 6-layer: signal/ground/signal/signal/ground/signal — two dedicated signal layers for routing with ground references on both sides. 8-layer: signal/ground/signal/power/ground/signal/ground/signal — supports higher density and multiple impedance targets. 10-12 layers and above: required for complex processors, FPGAs and high-pin-count BGAs where routing density exceeds what 8 layers can accommodate.

Material selection by layer

Not all layers need the same material. Hybrid stackups use low-loss laminates (Megtron 6/7) on high-speed signal layers and standard FR-4 on power planes and low-speed signal layers. RF hybrid stackups place Rogers or PTFE on RF signal layers and FR-4 on digital layers. The stackup calculator helps plan these mixed-material constructions by specifying different dielectric materials on each layer.

For production stackup engineering, request a quote with your impedance targets and layer count requirements. The engineering team will design and verify the stackup using field solver analysis with actual laminate data.