High Density Interconnect
HDI PCB: High Density Interconnect Manufacturing
High-density interconnect boards combine fine-pitch component escape, microvias and sequential construction choices. The strongest HDI plan is grounded in the actual routing, stack-up and reliability requirements of the design.
What is high density interconnect?
High density interconnect, usually shortened to HDI, describes PCB constructions that use finer features and more efficient interconnect strategies to create routing density beyond a conventional through-hole multilayer board. Common approaches include laser-drilled microvias, blind and buried vias, via-in-pad structures and sequential lamination.
HDI is not one fixed construction. The appropriate build depends on component pitch, routing congestion, required layer count, impedance control, thermal constraints, board thickness and the reliability requirements of the final product.
HDI construction decisions
- Microvia placement and whether vias are stacked or staggered
- Blind, buried and through-via strategy for each build-up layer
- Via-in-pad, filled-and-capped-via and BGA escape requirements
- Fine-line geometry, registration tolerance and plating considerations
- Sequential-lamination sequence and the effect on layer stack-up
- Material selection, impedance targets and signal-integrity constraints
Microvia, capped via and blind-via planning
Microvias
Laser-drilled microvias can create short, direct connections between adjacent layers. Their placement, size and stacking approach should be reviewed together with the sequential build-up plan.
Capped vias
Filled and capped vias are frequently used where pad real estate is limited or where component placement requires a planar surface. The drawing package should state the expected fill and cap construction clearly.
Blind and buried vias
Blind and buried vias can reduce routing congestion, but they also add process and registration considerations. Use the layer-stack drawing to state the start and stop layers for every controlled drill structure.
Prepare an HDI request for quote
A practical HDI package includes the current manufacturing data, a detailed stack-up or electrical targets, component pitch, smallest line and space, drill and microvia requirements, copper weights, finished thickness, impedance table, test requirements and target quantity. Highlight any feature that cannot be substituted.
Related resources
Megtron Materials
Explore high-speed material considerations.
Via in Pad Guide
Review one common HDI interconnect strategy.
AI & Data Center PCB
See an HDI-intensive application context.
AstroPCB-published capability data · Updated September 18, 2026
Engineering capability snapshot
These are published engineering reference points for quotation and early design planning. Final construction, tolerances and producibility are confirmed through DFM review against the actual stack-up, material, copper distribution and quantity.
| Capability | Published reference |
|---|---|
| HDI build-up | Up to 7-step HDI; stacked or staggered microvia strategies reviewed by DFM. |
| Heavy copper | Up to 10 oz copper for suitable FR-4 heavy-copper constructions. |
| Fine features | Published quotation range reaches 3 mil line/space and 0.10 mm mechanical drill, subject to construction review. |
| Impedance control | Controlled-impedance options to ±8%, with stack-up confirmation required. |
| Via and finish options | Epoxy-filled and capped vias; HASL, lead-free HASL, ENIG, hard gold, immersion silver, immersion tin and ENEPIG options. |
HDI construction is confirmed from the stack-up, not a generic rule
A 7-step HDI capability does not mean every design should use seven sequential build-ups. The DFM review matches the necessary build-up, via style and lamination sequence to the routing problem so complexity is purposeful.
- Use stacked microvias where density requires them and the reliability plan supports the structure.
- Use staggered microvias where routing and yield objectives make that approach more appropriate.
- Confirm drill, pad, capture-land and copper-distribution requirements against the final fabrication data.