HDI PCB Design Guidelines: From Stackup Planning to Microvia Optimization

High Density Interconnect (HDI) PCB design demands a different approach than conventional multilayer layout. With microvia diameters below 100μm, trace widths under 3 mil, and sequential lamination adding layers of manufacturing complexity, every design decision has a direct impact on yield, cost, and signal performance.

This guide covers the practical engineering decisions that separate a manufacturable HDI design from one that causes yield problems on the production floor. Whether you are routing your first BGA fanout on an HDI stackup or optimizing a 3+N+3 structure for volume production, these guidelines will help you avoid the most common and costly mistakes.

Understanding HDI Stackup Structures

HDI stackups are defined by their buildup notation: the number before N represents buildup layers on each side, and N is the conventional core layer count. A 1+N+1 structure has one microvia layer on each side of a standard multilayer core. A 2+N+2 has two sequential buildup layers per side, enabling stacked or staggered microvias.

The choice of HDI structure depends primarily on BGA escape requirements. For BGAs with 0.8mm pitch and 4-row perimeter routing, a 1+N+1 stackup often suffices — the single microvia layer provides enough via-in-pad connections to escape the outer two rows, while inner rows route through conventional buried vias in the core.

As BGA pitch decreases or a full-array pin map increases escape demand, a 2+N+2 structure may be needed. Confirm the layer requirement from the actual package pinout and routing study. The second buildup layer allows stacked microvias that connect surface pads to deeper routing layers without consuming horizontal routing space. This is the standard structure for smartphone application processors, FPGA packages, and advanced SoC designs.

For the most demanding applications — System-in-Package (SiP) modules, high-density interposers, and advanced wearable electronics — 3+N+3 through 7+N+7 structures provide the routing density needed to escape ultra-fine-pitch arrays below 0.4mm. Additional sequential laminations increase process complexity and cost. The increment depends on the stack-up, via structure, material, quantity and yield requirements, so confirm it in the project quote.

Microvia Design Rules That Affect Yield

The reliability of an HDI PCB depends heavily on microvia design. Laser-drilled microvias are typically 75-100μm in diameter with a 1:1 maximum aspect ratio (depth to diameter). A via outside the approved aspect ratio can create plating and reliability problems; review the actual dielectric depth, hole profile and fill process before release.

For standard single-layer microvias connecting layer 1 to layer 2, the math is straightforward: if your dielectric thickness is 75μm (3 mil), your minimum microvia diameter is 75μm. Most designers use 100μm (4 mil) microvias as a comfortable standard that provides manufacturing margin.

Stacked microvias introduce additional reliability considerations. When microvias are stacked directly on top of each other across multiple buildup layers, the bottom via in the stack experiences the most thermal stress during lamination and reflow. Copper filling the lower microvia must be solid and void-free, because any void becomes a crack initiation point during thermal cycling. AstroPCB recommends copper-filled and capped microvias for all stacked configurations, with cross-section verification on first articles.

Via-in-pad design requires the microvia to be filled flush with the pad surface and plated over to create a flat, solderable landing. Specify permitted dimpling and pad planarity against the component and assembly requirements. Agree on the fill/cap process and inspection criteria in the fabrication drawing.

Routing Strategies for HDI Layouts

HDI routing follows a fundamentally different philosophy than conventional PCB layout. In a standard multilayer board, routing starts on inner layers and uses through-hole vias to transition between layers. In HDI, routing starts from the surface (where BGAs and fine-pitch components sit) and works inward through microvia transitions.

The BGA fanout strategy determines the entire layer assignment approach. For a 0.65mm pitch BGA, the outer two rows can typically be fanned out on the surface layer using dog-bone vias or via-in-pad. Inner rows require microvias to layer 2, where traces route outward and then transition through buried vias to deeper layers. The number of BGA rows that can escape per routing layer determines the minimum HDI structure needed.

Impedance planning in HDI stackups must account for the thin dielectrics used in buildup layers. With dielectric thicknesses of 50-75μm (compared to 100-200μm in conventional multilayer cores), trace widths for 50Ω impedance are narrower — typically 2.5-3.5 mil on buildup layers versus 4-5 mil on core layers. This narrower trace width improves routing density but requires tighter manufacturing tolerances.

Differential pairs on HDI layers need careful spacing control. The tight coupling achievable on thin dielectric layers (pair-to-pair spacing of 3-4x the dielectric height) provides excellent noise rejection, but the narrow traces are more sensitive to etching variations. AstroPCB’s published controlled-impedance reference is ±8%, with field-solver modeling and TDR coupons. State the target for each impedance class; requirements outside this reference are reviewed per design.

Material Selection for HDI Stackups

Buildup layers in HDI PCBs typically use resin-coated copper (RCC) foil or thin prepreg with low-flow characteristics. The dielectric material must have a stable Dk value (important for impedance consistency across the board area) and good laser drilling characteristics (clean via formation without residue).

Modified FR-4 may suit an HDI design where channel loss and thermal requirements permit it; confirm suitability through the electrical and manufacturing review. For high-speed HDI, compare low-loss materials such as the Megtron family against the actual channel length, loss budget, copper profile and test frequency. Data rate alone does not establish a suitable grade.

Core materials in the N section of the stackup can be standard FR-4 for non-critical layers, with low-loss materials reserved for layers carrying high-speed signals. A hybrid can reduce material cost, but material compatibility, lamination sequence and the actual saving must be confirmed for the proposed construction.

DFM Checklist for HDI Designs

Before submitting your HDI design for fabrication, verify these critical parameters that directly affect manufacturing yield and cost:

First, confirm that all microvia aspect ratios are within 1:1. Check not just the nominal ratio but also the worst-case ratio accounting for dielectric thickness tolerances. Second, verify that stacked microvias are specified as copper-filled — unfilled stacked microvias are a reliability risk that most reputable manufacturers will flag during DFM review.

Third, check your annular ring dimensions. Confirm capture-pad dimensions and annular rings against the via size, registration allowance and approved process; the minimum laser diameter alone does not define an acceptable pad. Fourth, ensure your fabrication notes specify the HDI structure explicitly (e.g., “2+8+2, stacked microvias, copper filled”) rather than relying on the manufacturer to interpret your layer stack drawing.

Finally, provide a comprehensive stackup table showing dielectric materials, thicknesses, copper weights, and impedance targets for every layer. HDI stackup tables are more complex than conventional boards because buildup layers use different materials and thicknesses than core layers. An unambiguous stack-up helps prevent incompatible assumptions during first-article fabrication.

Get Expert HDI Design Support

See the HDI PCB manufacturing service for process details and the 26-layer HDI engineering case for a documented construction example.

AstroPCB’s published manufacturing capabilities include up to 7 sequential laminations, 75 µm minimum laser drill with aspect ratio up to 1:1, 0.10 mm minimum mechanical drill, 50/50 µm minimum line/space and ±8% controlled impedance. Total PCB layer count is 1–30; the HDI construction is confirmed from the stack-up during DFM. Every order includes free DFM review by our HDI engineering team, who will verify your stackup, via structures, and routing compatibility with our process capabilities before production begins.

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Related guides: Via Types and Manufacturing Capabilities · Stack-up Calculator and Planning Guide · Controlled Impedance Capability