Case study · Any-layer HDI · 5G sensing & control
Any-Layer HDI PCB Case Study: 26 Layers, 12 Laser Cycles on TU-933+
A 26-layer any-layer HDI board on TU-933+ low-loss laminate for a 5G high-speed remote sensing and measurement-control product. Every layer pair is connected by laser microvias, built with 12 laser drill and fill cycles on 0.1 mm thin cores.
- Layer count
- 26 L
- Laser drill / fill cycles
- 12×
- Thin core
- 0.1 mm
- Laser fill flatness
- ≤25 µm
Overview
What this any-layer HDI project is.
An any-layer HDI PCB (also called ELIC, every-layer interconnect) connects any two adjacent layers with laser-drilled, copper-filled microvias, so routing is no longer limited to fixed via spans. In this AstroPCB project, a 26-layer any-layer board was built on TU-933+ using 12 laser drill and copper-fill cycles.
| Parameter | This build |
|---|---|
| Layer count | 26 layers |
| Structure | Any-layer laser blind vias (every layer pair) |
| Laminate | TUC TU-933+ low-loss system |
| Laser drill / copper fill cycles | 12 |
| Thin core | 0.1 mm |
| Laser via fill flatness | ≤ 25 µm |
| End product | 5G high-speed remote sensing measurement & control |
| Order range | Samples and small batch |
Key takeaways
- Any-layer HDI removes fixed via spans: any adjacent layer pair can be connected by a stacked, copper-filled microvia.
- Twelve laser cycles means twelve rounds of drilling, filling and lamination, so dimensional control across cycles decides yield.
- Fill flatness (≤25 µm here) matters because each filled via becomes the landing pad for the next stacked via.
The challenge
Why this board needed any-layer HDI.
High-speed sensing and measurement-control electronics for 5G pack fine-pitch processors, high-speed converters and RF-adjacent interfaces into a small footprint. With 26 layers, a conventional HDI build with fixed blind-via spans would have forced long via stubs or extra through-holes in the most congested routing areas. The designer needed to drop from any layer to any other layer directly under the component pins, which is what an any-layer structure allows.
Three requirements set the difficulty. First, the board had to stay electrically consistent on a low-loss laminate (TU-933+) through many lamination cycles. Second, every one of the 12 laser-via levels had to land on the filled via below it, which needs tight registration from the first cycle to the last. Third, thin 0.1 mm cores had to stay flat and dimensionally stable while being handled, drilled and pressed repeatedly.
Stack-up
Stack-up and via structure.
The stack-up drawing for this build shows a thin central core with build-up dielectric layers added symmetrically on both sides, one pair per lamination cycle. Each build-up layer carries laser-drilled microvias that are copper-filled and planarised before the next layer is laminated on top, so the vias can be stacked through the full thickness or offset layer by layer as routing requires.
| Element | Detail |
|---|---|
| Total layers | 26 (L1–L26) |
| Laminate family | TU-933+ cores and matching prepregs throughout |
| Core | 0.1 mm thin core at the centre of the stack |
| Build-up sequence | Symmetric build-up layers added in 12 laser drill / fill cycles |
| Via type | Laser blind microvias, copper filled, stackable at any layer |
| Via fill requirement | Flatness (dimple / bump) ≤ 25 µm |
TU-933+ is a low-loss laminate system from Taiwan Union Technology (TUC) used in high-speed digital and telecom boards. Exact Dk and Df depend on resin content and glass style, so the values used for impedance modelling are taken from the laminate datasheet for each construction (typical, confirm with datasheet).
How we built it
Core manufacturing technologies.
Any-step plating fill control
Every laser via is filled with electroplated copper and planarised so it can carry the next via. Fill flatness is held to ≤25 µm; voids or deep dimples would weaken the stacked joint above.
Blind-via scaling control at any step
Material moves slightly with every press cycle. Scaling (expansion and shrinkage) is measured and compensated per cycle so the 12th laser level still lands on the pads of the first.
Microvia capabilityThin-core handling
0.1 mm cores are processed with support and controlled lamination profiles to limit distortion, which feeds directly into registration across all 12 cycles.
HDI PCBThe build therefore repeats one loop twelve times: laminate a new dielectric layer, laser drill, desmear, metallise, copper fill, planarise, image and etch. Measuring scaling after every press and correcting the drill and imaging data is what keeps a stacked via aligned through the full stack. This is the main difference between any-layer HDI and ordinary 1–3 step HDI.
Verification
How builds like this are verified.
- Microsection after selected cycles to check fill, dimple and stacked-via interfaces
- Registration checks of each build-up level (X-ray / coupon)
- Bare-board electrical test (flying probe or fixture) against the netlist
- Impedance coupons measured by TDR where impedance is specified
- Microsection of coupons to confirm microvia fill, plating and layer registration
- Visual and dimensional inspection to IPC-A-600 for the specified class
Design takeaways
Design notes for your own any-layer HDI board.
- Decide early whether you need true any-layer or whether 3–4 step stacked HDI covers the breakout; any-layer adds lamination cycles and cost.
- Keep the stack-up symmetric so the board stays flat across many press cycles.
- Specify the fill requirement for stacked vias (for example dimple ≤ 25 µm) on the fabrication drawing.
- Use one laminate system for cores and prepregs to keep CTE and press behaviour consistent.
- Share impedance targets per layer; thin dielectrics make trace widths very sensitive to Dk and thickness.
- Ask for a stack-up proposal before routing; via spans and dielectric thickness are hard to change later.
Related reading: blind and buried vias, via in pad and the stack-up calculator.
Comparison
Any-layer HDI vs conventional stacked HDI.
| Conventional 1–3 step HDI | Any-layer HDI (this build) | |
|---|---|---|
| Via spans | Fixed blind spans on outer build-up layers | Any adjacent layer pair |
| Lamination cycles | 1–3 per side typical | Many; 12 laser cycles here |
| Routing freedom | Limited by span plan | Highest |
| Cost and lead time | Lower | Higher; justified by density |
| Typical use | Most BGA breakout | Very dense, compact high-speed products |
Quote a similar build
What to send for an any-layer HDI quote.
- Gerber, ODB++ or IPC-2581 data with drill files for every via span
- Target stack-up, laminate preference (e.g. TU-933+) and finished thickness
- Impedance targets per layer and reference planes
- Stacked-via fill and flatness requirements
- IPC class, quantities (samples / small batch) and schedule
Upload files on the quote page; every quote includes a written DFM and stack-up review.
FAQ
Questions about this build.
What is an any-layer HDI PCB?
An any-layer (ELIC) HDI PCB connects any two adjacent layers with laser-drilled, copper-filled microvias, so vias can be stacked or offset at every layer instead of following fixed blind-via spans.
How many layers did this any-layer HDI board have?
26 layers, built with 12 laser drill and copper-fill cycles on TU-933+ laminate with 0.1 mm thin cores.
Why does copper fill flatness matter?
Each filled microvia becomes the landing pad for the next stacked via. This build held fill flatness to ≤25 µm so stacked joints stay reliable.
What is TU-933+?
A low-loss laminate system from Taiwan Union Technology (TUC) used for high-speed digital and telecom boards. Use the datasheet values for impedance modelling.
Is any-layer HDI more expensive than standard HDI?
Yes. Each laser cycle adds a lamination, drilling and plating loop, so cost and lead time rise with the number of cycles. It is worth it when routing density demands it.
What order quantities do you accept for this type of board?
Samples and small batches, with the same stack-up and process controls for each lot.
Can you review my stack-up before layout?
Yes. Send a target stack-up or reference design for a free stack-up and DFM review before routing starts.
Ready when your files are
Building a similar board? Send it for a stack-up review.
Upload Gerber, ODB++ or IPC-2581 data. Every quote includes a written engineering DFM review, typically within one business day.