Case study framework · HDI
AI Accelerator PCB with HDI: Design & Build Framework
How a 30-layer AI accelerator board with 0.4–0.5 mm BGAs is made buildable: stacked microvias, lamination count, Megtron laminate and 500–700 W power delivery.
BGA escape
BGA escape at 0.4–0.65 mm pitch.
An AI accelerator PCB typically has 30-layers, BGAs with 4,000–10,000+ balls at 0.4–0.5 mm pitch, 56–112G PAM4 channels and power rails feeding 500–700 W. Escape routing relies on via-in-pad microvias, often stacked two or three levels.
See microvia and via in pad.
Lamination
Lamination cycles drive cost.
A 30-layer board with 3-level stacked microvias needs five or more sequential laminations. Escaping with 2-level stacks instead of 3 saves a cycle per side, which can cut fabrication cost by roughly 20–30%. Plan layer assignment early. See HDI PCB.
Laminate
Laminate for 56G and 112G.
Megtron 6 suits 56G PAM4 at short-to-medium reach; Megtron 7 suits longer 56G channels and 112G. Validate with channel simulation on the real stack-up. See Megtron.
Sequential lamination and build-up structure
Sequential lamination and build-up structure.
Core layers are fabricated first (drilled, plated and etched) and laminated into a sub-assembly. Build-up layers are then added in pairs, one on each side, and every lamination is followed by laser drilling and plating to connect the new layers. A 30-layer board with three-level stacked microvias typically needs five or more lamination cycles. Each cycle adds material, press time and yield risk, which is why it costs so much.
Signal integrity
Channel design for 56G/112G.
Beyond laminate, channels are shaped by copper roughness (HVLP foil), glass weave (spread glass to limit skew), via stubs (back-drilling) and transitions at the package and connector. Validate with channel simulation on the actual stack-up and via models before release. See high speed PCB.
Thermal
Thermal and mechanical considerations.
With hundreds of watts in a small area, thermal-via arrays under the package move heat into internal planes and toward cold plates. Thick boards (often 3–5 mm) with many heavy planes need balanced copper to stay flat through reflow and press-fit insertion. Large panels need tight registration and warpage control.
| Risk | Mitigation |
|---|---|
| Warp on thick boards | Balanced copper, symmetric stack-up |
| Resin starvation between heavy planes | Prepreg selection, press profile |
| Microvia separation | ≤1:1 aspect ratio, staggered where possible |
| Via stub resonance | Back-drill to specified depth |
Design for manufacture
Design choices that control cost and yield.
Lamination cycles, board thickness and hole count drive most of the cost. Prefer two-level stacked or staggered microvias over three-level stacks where breakout allows, keep the number of distinct blind-via spans low, hold through-hole aspect ratio within published limits, and use back-drilling rather than extra thickness to manage stubs. Each of these choices reduces cost and improves yield on a 30-layer board.
- Minimize lamination cycles
- Limit distinct via spans
- Respect through-hole aspect ratio limits
- Balance copper across the stack
- Specify back-drill depth and keep-out per net
Materials
Material choices for accelerator boards.
| Layer group | Typical material |
|---|---|
| SerDes signal layers | Megtron 7 / 8 with HVLP copper |
| Power and ground planes | Megtron or compatible high-Tg FR-4 in hybrids |
| Build-up (HDI) layers | Laser-drillable low-loss prepreg |
Verification
How an accelerator build is verified.
- TDR impedance on coupons per panel
- Microsection of stacked microvias and back-drill depth
- X-ray registration across large panels
- Warpage measurement after lamination and simulated reflow
- 100% electrical test, including high-pin-count nets
These checks give the evidence that a 30-layer HDI board was built to its stack-up, which matters when a channel or power issue later has to be traced to design or fabrication.
Power delivery
Power delivery for 500–700 W processors.
- 3–4 oz power and ground planes
- Dense power via arrays at the package
- IR-drop analysis on the actual layout
- Heavy copper where needed
FAQ
Common questions.
How many layers does an AI accelerator PCB have?
Commonly 20–30 layers for large accelerators.
Which laminate for 112G?
Megtron 7 or similar ultra-low-loss laminates.
How many lamination cycles does an AI board need?
Often five or more for 30-layers with three-level stacked microvias; fewer with two-level or staggered structures.
How do you control warp on thick boards?
Balanced copper, symmetric stack-ups and controlled lamination profiles.
What power do these boards handle?
Accelerators commonly draw 500–700 W, needing heavy power planes and dense via arrays.
Do you simulate channels?
We provide stack-up and impedance data for your channel simulation and review via structures and back-drill depth in DFM.
Ready when your files are
Send your design for an engineering review.
Upload Gerber, ODB++ or IPC-2581 data. Every quote includes a written engineering DFM review, typically within one business day.